Comparative Review of Binary Multiplier Systems
AUTHORS
Marcus Lloyde George,Department of Electrical and Computer Engineering University of West Indies, St. Augustine, Trinidad and Tobago
Geetam Singh Tomar,THDC Institute of Hydropower Engineering and Technology, Bhagirathipuram, Tehri 249 124 India
ABSTRACT
This paper presents a comprehensive comparative review of existing 8-bit, 16-bit and 24-bit binary multiplier architectures and seeks to identify engineering techniques involved in their development. A comparison of the performance of these systems in terms of metrics such as path delay, hardware utilization and even power consumption in some case are carried out. Weaknesses in the systems reviewed along with possible gaps in the area of research are identified. This paper also serves to identify several recommendations and considerations for the development of a multi-precision binary multiplier system capable of treating with the weaknesses of multiplier systems identified.
KEYWORDS
Binary Multiplier, Path Delay, Hardware Utilisation,Multi precision Multiplier
REFERENCES
[1] Kodali, Ravi Kishore, Lakshmi Boppana, and Sai Sourabh Yenamachintala. 2015. “FPGA Implementation of Vedic Floating-Point Multiplier”. IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems (SPICES), 19-21 February, 2015, 1-4. New York: IEEE. (2015) DOI: 10.1109/SPICES.2015.7091534.(CrossRef)(Google Scholar)
[2] Sharma, Richa, Manjit Kaur, and Gurmohan Singh. 2015. “Design and FPGA Implementation of Optimized 32-Bit Vedic Multiplier and Square Architectures”. International Conference on Industrial Instrumentation and Control (ICIC), 28-30 May, 2015, 960-964. New York: IEEE. (2015) DOI: 10.1109/IIC.2015.7150883.(CrossRef)(Google Scholar)
[3] Anitha, P., and P. Ramanathan. 2014. “A New Hybrid Multiplieusing Dadda and Wallace Method”. International Conference on Electronics and Communication Systems (ICECS), 13-14 February, 2014, 1-4. New York: IEEE. (2014) DOI: 10.1109/ECS.2014.6892623.(CrossRef)(Google Scholar)
[4] Abraham, Sumod, Sukhmeet Kaur, and Shivani Singh. 2015. “Study of Various High Speed Multipliers”. International Conference on Computer Communication and Informatics (ICCCI), 8-10 January, 2015, 1-5. New York: IEEE. (2015) DOI: 10.1109/ICCCI.2015.7218139.(CrossRef)(Google Scholar)
[5] Vyas, Keerti, Ginni Jain, Vijendra K. Maurya, and Anu Mehra. 2015. “Analysis of an Efficient Partial Product Reduction Technique”. International Conference on Green Computing and Internet of Things (ICGCIoT), 8-10 October, 2015, 1-6. New York: IEEE. (2015) DOI: 10.1109/ICGCIoT.2015.7380417. (CrossRef)(Google Scholar)
[6] Chopade, S. S., and Rama Mehta. 2015. “Performance Analysis of Vedic Multiplication Technique using FPGA”. IEEE Bombay Section Symposium (IBSS), 10-11 September 2015, 1-6. New York: (2015) IEEE. DOI: 10.1109/IBSS.2015.7456657. (CrossRef)(Google Scholar)
[7] Bisoyi, Abhyarthana, Mitu Baral, and Manoja Kumar Senapati. 2014. “Comparison of a 32-bit Vedic Multiplier with a Conventional Binary Multiplier”. International Conference on Advanced Communication Control and Computing Technologies (ICACCCT), 8-10 May, 2014, 1757-1760. New York: IEEE. (2014) DOI: 10.1109/ICACCCT.2014.7019410.(CrossRef)(Google Scholar)
[8] Mhaidat, Khaldoon M., and Abdulmughni Y. Hamzah. 2014. “A New Efficient Reduction Scheme to Implement Tree Multipliers on FPGAs”. 9th International Design and Test Symposium, 16-18 December, 2014, 180-184. New York: IEEE. (2014) DOI: 10.1109/IDT.2014.7038609.(CrossRef)(Google Scholar)
[9] Bathija, R.K., R.S. Meena, S. Sarkar, and Rajesh Sahu. 2012. “Low Power High Speed 16x16 bit Multiplier using Vedic Mathematics”. International Journal of Computer Applications 59 (6): 41-44. (2012)(CrossRef)(Google Scholar)
[10] Rao, Jagadeshwar M., and Sanjay Dubey. 2012. “A High Speed and Area Efficient Booth Recoded Wallace Tree Multiplier for Fast Arithmetic Circuits”. Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PRIMEASIA), 5-7 December 2012, 220-223. New York: IEEE. (2012) DOI: 10.1109/PrimeAsia.2012.6458658.(CrossRef)(Google Scholar)
[11] Jain, Anna, Baisakhy Dash, Ajit Kumar Panda, and Muchharla Suresh, “FPGA Design of a Fast 32-bit Floating-Point Multiplier Unit”. International Conference on Devices, Circuits and Systems (ICDCS), 15-16 March 2012, 545-547. New York: IEEE (2012)(CrossRef)(Google Scholar)
[12] Arish, S., and R. K. Sharma, “Run-Time Reconfigurable Multi-Precision Floating-Point Multiplier Design for High Speed, Low-Power Applications”. 2nd International Conference on Signal Processing and Integrated Networks (SPIN), 19-20 February, 2015, 902-907. New York: (2015) DOI: 10.1109/SPIN.2015.7095315.(CrossRef)(Google Scholar)
[13] Arish, S., and R. K. Sharma “An Efficient Binary Multiplier Design for High Speed Applications using Karatsuba Algorithm and Urdhva-Tiryagbhyam Algorithm”. Global Conference on Communication Technologies (GCCT), 23-24 April, 2015, 192-196. New York: IEEE. (2015) DOI: 10.1109/GCCT.2015.7342650.(CrossRef)(Google Scholar)
[14] Gokhale, G. R., and P. D. Bahirgonde, “Design of Vedic-Multiplier using Area-Efficient Carry Select Adder”. International Conference on Advances in Computing, Communications and Informatics (ICACCI), 10-13 August 2015, 576-581. New York: IEEE. (2015) DOI: 10.1109/ICACCI.2015.7275671.(CrossRef)(Google Scholar)
[15] Ram, G. Challa, Y. Rama Lakshmanna, D. Sudha Rani, and K.Bala Sindhuri. 2016. “Area Efficient Modified Vedic Multiplier”. International Conference on Circuit and Computing Technologies (ICCPCT), 18-19 March, 2016, 276-279. New York: IEEE. (2016) DOI: 10.1109/ICCPCT.2016.7530294.(CrossRef)(Google Scholar)
[16] Thapliyal, Himanshu, and M. B. Srinavas. 2005. “A Novel Time-Area-Power Efficient Single Precision Floating Multiplier”. Proceedings of MAPLD 16-18 June, 2005, 1-3. New York: IEEE (2005).
[17] Gupta, Aman, Satyam Mandavalli, Vincent J. Mooney, Keck-Voon Ling, Arindam Basu, Henry Johan, and Budianto Tandianus. 2011. “Low Power Probabilistic Floating-Point Multiplier Design”. 2011 IEEE Computer Society Annual Symposium on VLSI, 4-6 July, 2011, 182-187. New York: IEEE. (2011) DOI: 10.1109/ISVLSI.2011.54.(CrossRef)(Google Scholar)
[18] IEEE (Institute of Electrical and Electronic Engineers). 2008. 754-2008 - IEEE Standard for Floating-Point Arithmetic. Revision of ANSI/IEEE Std 754-1985. New York: IEEE (2008).
[19] George, Marcus, and Geetam Singh Tomar. 2015. “Hardware Design Procedure: Principles and Practices”. 5th International Conference on Communication Systems and Network Technologies, 4-6 April, 2015, 834 - 838. New York: IEEE. (2015) DOI: 10.1109/CSNT.2015.198.(CrossRef)(Google Scholar)
[20] Hambley, Allan. 2001. Electrical Engineering Principles and Applications. 2nd. ed. New Jersey: Prentice Hall (2001).
[21] Anane, N., H. Bessalah, M. Issad, and M. Anane. 2009. “Hardware Implementation of Variable Precision Multiplication on FPGA”. 4th International Conference Design & Technology of Integrated Systems in Nanoscal Era, 6-9 April, 2009, 77-81. New York: IEEE. (2009) DOI: 10.1109/DTIS.2009.4938028.(CrossRef)(Google Scholar)
[22] Benini, L., and G. D. Micheli. 1996. “Automatic Synthesis of Low-Power Gated Clock Finite-State Machines”. IEEE Transactions on CAD 15 (6): 630–643 (1996).(CrossRef)(Google Scholar)
[23] Cheng, Fu-Chiung, Stephen H. Unger, Michael Theobald, and Wen-Chung Cho. 1997. “Delay-Insensitive Carry-Look Ahead Adders”. Proceedings of 10th International Proceedings VLSI Design, Conference, 4-7 January, 1997. 37-63. New York: IEEE (1997).(CrossRef)(Google Scholar)
[24] Hennessey, John, and David Patterson. 2003. Computer Architecture. A Quantitative Approach. 3rd ed. San Francisco: Morgan Kaufmann Publishers (2003).
[25] Kattamuri, R.S.N. Kumar, and S. K. Sahoo. 2010. “Computation Sharing Multiplier Using Redundant Binary Arithmetic”. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 6-9 December 2010, 108-111. New York: IEEE. (2010) DOI: 10.1109/APCCAS.2010.5774869.(CrossRef)(Google Scholar)
[26] GS Tomar, Marcus George, “Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization”, Springers Wireless Personal Communication, vol.98, no.4, pp.3554-3561, (2018)(CrossRef)(Google Scholar)
CITATION
COPYRIGHT
© 2018 George Marcus Lloyde et al.. Published by Global Vision Press. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 International License (CCBY4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.