An Automatic Array Distribution Technique for Multi-Bank Memory of High Performance IoT Systems
AUTHORS
Jungseok Cho,Computer Engineering, Yeungnam Univ., South Korea
Jonghee M. Youn,Electrical & Electronic Engineering, Sunchon National Univ., South Korea
Doosan Cho,Electrical & Electronic Engineering, Sunchon National Univ., South Korea
ABSTRACT
Mobile devices designed for IoT exploit a variety of system optimization techniques to maximize performance while reducing power consumption. These technologies apply to communication modules, to memory system, and to the central processing unit. Most of the technologies are developed and applied at the design stage of the system, but not many technologies are applied at the system integration stage. In the system integration stage, the major power consuming parts are the communication part and the memory part. Since communication has a lot of variables depending on the network environment, there are some limited technologies available, but in the case of memory, a large benefit can be obtained depending on the technology applied. Mobile or IoT system’s memory structures can be classified in many different ways, of which we focus on multi-bank memory. Multi-bank memory refers to a method of dividing a large memory into several smaller memories. Using multi-bank memory can reduce operating power consumption and support parallel memory accesses, resulting in improved performance, which is often used in commercial products. A compiler should generate the access instruction and data placement properly. Therefore, the system performance is determined by the compiler performance. In this paper, we introduce a compiler optimization technique for multi-bank memory to overcome the compiler performance. The proposed technique can improve energy consumption by up to 20% in multi-bank memory systems.
KEYWORDS
Energy consumption, IoT system, Multi-bank memory, Memory structure, Compiler technique, System optimization
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