KEYWORDS

Arithmetic Logic Unit, Floating-Point Multiplier, Multi-Precision Floating Point, Multiplier System, Multiplier Architecture, FPGAs in Arithmetic

REFERENCES

[1]     Kodali, Ravi Kishore, Lakshmi Boppana, and Sai Sourabh Yenamachintala. (2015). “FPGA Implementation of Vedic Floating-Point Multiplier”. IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems (SPICES), 19-21 February, 2015, 1-4. New York: IEEE. DOI: 10.1109/SPICES.2015.7091534.(CrossRef)(Google Scholar)
[2]     Arish, S., and R. K. Sharma. 2015a. “Run-Time Reconfigurable Multi-Precision Floating-Point Multiplier Design for High Speed, Low-Power Applications”. 2nd International Conference on Signal Processing and Integrated Networks (SPIN), 19-20 February, (2015), 902-907. New York: IEEE. DOI: 10.1109/SPIN.2015.7095315.(CrossRef)(Google Scholar)
[3]     Arish, S., and R. K. Sharma. (2015) 2015b. “An Efficient Binary Multiplier Design for High Speed Applications using Karatsuba Algorithm and Urdhva-Tiryagbhyam Algorithm”. Global Conference on Communication Technologies (GCCT), 23-24 April, 2015, 192-196. New York: IEEE. DOI: 10.1109/GCCT.2015.7342650.(CrossRef)(Google Scholar)
[4]     Even, G., S. M. Mueller, and P. M. Seidel. (1997). “A Dual Mode IEEE Multiplier”. Proceedings of 2nd Annual IEEE International Conference on Innovative Systems in Silicon, 8-10 October, 1997, 282-289. New York: IEEE. DOI: 10.1109/ICISS.1997.630271. (CrossRef)(Google Scholar)
[5]     Sharma, Richa, Manjit Kaur, and Gurmohan Singh. (2015). “Design and FPGA Implementation of Optimized 32-Bit Vedic Multiplier and Square Architectures”. International Conference on Industrial Instrumentation and Control (ICIC), 28-30 May, 2015, 960-964. New York: IEEE. DOI: 10.1109/IIC.2015.7150883.(CrossRef)(Google Scholar)
[6]     Anitha, P., and P. Ramanathan. (2014). “A New Hybrid Multiplieusing Dadda and Wallace Method”. International Conference on Electronics and Communication Systems (ICECS), 13-14 February, 2014, 1-4. New York: IEEE. DOI: 10.1109/ECS.2014.6892623.(CrossRef)(Google Scholar)
[7]     Sunesh, N.V, and P Sathishkumar. (2015). “Design and Implementation of Fast Floating-Point Multiplier Unit”. International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), 8-10 January 2015, 1-5. New York: IEEE. DOI: 10.1109/VLSI-SATA.2015.7050478.(CrossRef)(Google Scholar)
[8]     IEEE (Institute of Electrical and Electronic Engineers). (2008). 754-2008 - IEEE Standard for Floating-Point Arithmetic. Revision of ANSI/IEEE Std 754-1985. New York: IEEE.
[9]     Cui, Xiaoping, Weiqiang Liu, Xin Chen, Earl Swartzlander, and Fabrizio Lombardi. (2015). “A Modified Partial Product Generator for Redundant Binary Multipliers”. IEEE Transactions on Computers 65 (4): 1165 – 1171. DOI: 10.1109/TC.2015.2441711.(CrossRef)(Google Scholar)
[10]  Huntsman, C., and D. Cawthron. (1983). “The MC68881 Floating-Point Coprocessor”. IEEE Micro 3 (6): 44-54. DOI: 10.1109/MM.1983.291185.(CrossRef)(Google Scholar)
[11]  Thapliyal, Himanshu, and M. B. Srinavas. (2005). “A Novel Time-Area-Power Efficient Single Precision Floating Multiplier”. Proceedings of MAPLD 16-18 June, 2005, 1-3. New York: IEEE.
[12]  Siddamal, Saroja V., R. M. Banakar, and B. C. Jinaga. 2008. (2008). DELTA 2008. “Design of High-Speed Floating-Point Multiplier”. 4th IEEE International Symposium on Electronic Design, Test and Applications, 23-25 January, 2008, 285-289, New York: IEEE. DOI: 10.1109/DELTA.2008.19.(CrossRef)(Google Scholar)
[13]  Nachtigal, Michael, Himanshu Thapliyal, and Nagarajan Ranganathan. (2010). “Design of a Reversible Single Precision Floating-Point Multiplier based on Operand Decomposition”. 10th IEEE Conference on Nanotechnology (IEEE-NANO), 17-20 August, (2010), 233-237. New York: IEEE. DOI: 10.1109/NANO.2010.5697746.(CrossRef)(Google Scholar)
[14]  Al-Ashrafy, Mohamed, Ashraf Salem, and Wagdy Anis. (2011). “An Efficient Implementation of Floating-Point Multiplier”. Saudi International Electronics, Communications and Photonics Conference (SIECPC), 24-26 April, 2011, 1-5. New York: IEEE. DOI: 10.1109/SIECPC.2011.5876905.(CrossRef)(Google Scholar)
[15]  MG (Mentor Graphics). (2010). Precision Synthesis User’s Manual. Ottawa: MG.
[16]  Mehta, Anand, C. B. Bidhul, Sajeevan Joseph, and P. Jayakrishnan. (2013). “Implementation of Single Precision Floating-Point Multiplier using Karatsuba Algorithm”. International Conference on Green Computing, Communication and Conservation of Energy (ICGCE), 3-5 November, 2004, 254-256, New York: IEEE. DOI: 10.1109/ICGCE.2013.6823439.(CrossRef)(Google Scholar)
[17]  Paldurai, K., and K. Hariharan. (2015). “FPGA Implementation of Delay Optimized Single Precision Floating-Point Multiplier”. International Conference on Advanced Computing and Communication Systems, 5-7 January, 2015, 1-5. New York: IEEE. DOI: 10.1109/ICACCS.2015.7324094.(CrossRef)(Google Scholar)
[18]  Mano, M. Morris, and Charles R. Kime. (1997). Logic and Computer Design Fundamentals. New Jersey: Prentice Hall.
[19]  Gupta, Aman, Satyam Mandavalli, Vincent J. Mooney, Keck-Voon Ling, Arindam Basu, Henry Johan, and Budianto Tandianus. (2011). “Low Power Probabilistic Floating-Point Multiplier Design”. 2011 IEEE Computer Society Annual Symposium on VLSI, 4-6 July, 2011, 182-187. New York: IEEE. DOI: 10.1109/ISVLSI.2011.54.(CrossRef)(Google Scholar)
[20]  Beohar, Salty, and Sandip Nemade. (2016). “VHDL Implementation of Self-Timed 32-Bit Floating-Point Multiplier with Carry Look Ahead Adder”. International Conference on Advanced Communication Control and Computing Technologies (ICACCCT), 25-27 May, 2016, 772-775. New York: IEEE. DOI: 10.1109/ICACCCT.2016.7831743.(CrossRef)(Google Scholar)
[21]  Cheng, Fu-Chiung, Stephen H. Unger, Michael Theobald, and Wen-Chung Cho. (1997). “Delay-Insensitive Carry-Look Ahead Adders”. Proceedings of 10th International Proceedings VLSI Design, Conference, 4-7 January, 1997. 37-63. New York: IEEE.
[22]  Jaiswal, Manish Kumar, C. Ray, and C. Cheung. (2012). “Area-Efficient FPGA Implementation of Quadruple Precision Floating-Point Multiplier”. IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 21-25 May, 2012, 376-382. New York: IEEE. DOI: 10.1109/IPDPSW.2012.46.(CrossRef)(Google Scholar)
[23]  Ramesh, Addanki Purna, A. V. N. Tilak, and A. M. Prasad. (2013). “An FPGA-based High Speed IEEE-754 Double Precision Floating-Point Multiplier using Verilog”. International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), 7-9 January, 2013, 1-5. New York: IEEE. DOI: 10.1109/ICEVENT.2013.6496575.(CrossRef)(Google Scholar)
[24]  Rao, Y. Srinivasa, M. Kamaraju, and D. V. S. Ramanjaneyulu. (2015). “An FPGA Implementation of High Speed and Area Efficient Double-Precision Floating-Point Multiplier using Urdhva Tiryagbhyam Technique”. Conference on Power, Control, Communication and Computational Technologies for Sustainable Growth (PCCCTSG), 11-12 December 2015, 271- 276. New York: IEEE. DOI: 10.1109/PCCCTSG.2015.7503923.(CrossRef)(Google Scholar)
[25]  Shanmugapriyan, S., and K. Sivanandam. (2015). “Area Efficient Run Time Reconfigurable Architecture for Double Precision Multiplier”. IEEE 9th International Conference on Intelligent Systems and Control (ISCO), 9-10 January, 2015, 1-6. New York: IEEE. DOI: 10.1109/ISCO.2015.7282355.(CrossRef)(Google Scholar)
[26]  Lei, Kang, and Yan Xiao-Ying. (2014). “Design and Implementation for Quadruple Precision Floating-Point Multiplier Based on FPGA with Lower Resource Occupancy”. 5th International Conference on Intelligent Systems Design and Engineering Applications (ISDEA), 15-16 June, 2014, 326-329. New York: IEEE. DOI: 10.1109/ISDEA.2014.80.(CrossRef)(Google Scholar)
[27]  Havaldar, Soumya, and K S Gurumurthy. (2016). “Design of Vedic IEEE 754 Floating-Point Multiplier”. IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT). 20-21 May, 2016, 1131-1135. New York: IEEE. DOI: 10.1109/RTEICT.2016.7808008.(CrossRef)(Google Scholar)
[28]  Anane, N., H. Bessalah, M. Issad, and M. Anane. (2009). “Hardware Implementation of Variable Precision Multiplication on FPGA”. 4th International Conference Design & Technology of Integrated Systems in Nanoscal Era, 6-9 April, 2009, 77-81. New York: IEEE. DOI: 10.1109/DTIS.2009.4938028.(CrossRef)(Google Scholar)
[29]  Manolopoulos, K., D. Reisis, and V. A. Chouliaras. (2011). “An Efficient Multiple Precision Floating-Point Multiplier”. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 11-14 December 2011, 153-156. New York: IEEE. DOI: 10.1109/ICECS.2011.6122237.(CrossRef)(Google Scholar)
[30]  Jaiswal, Manish Kumar, and Hayden K. H. So. (2015). “Dual-Mode Double Precision / Two-Parallel Single Precision Floating-Point Multiplier Architecture”. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 5-7 October, 2015, 213-218. New York: IEEE. DOI: 10.1109/VLSI-SoC.2015.7314418.(CrossRef)(Google Scholar)
[31]  Mangalath, Nithu. S., R. Arokia Priya, and P. Malathi. (2014). “An Efficient Universal Multi-Mode Floating-Point Multiplier using Vedic Mathematics”. International Conference on Advances in Communication and Computing Technologies (ICACACT), 10-11 August, 2014, 1-4, New York: IEEE. DOI: 10.1109/EIC.2015.7230724.(CrossRef)(Google Scholar)
[32]  Liu, De, Mingjiang Wang, Yiwen Wang, and Hang Su. (2015). “A Multi-Functional Floating-Point Multiplier”. IEEE 9th International Conference on Anti-counterfeiting, Security, and Identification (ASID), 25-27 September, 2015, 56-60, New York: IEEE. DOI: 10.1109/ICASID.2015.7405661.(CrossRef)(Google Scholar)
[33]  Jaiswal, Manish Kumar, and Hayden K. H. So. (2016). “Architecture for Quadruple Precision Floating-Point Division with Multi-Precision Support”. IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 6-8 July, 2016, 239-240. New York: IEEE. DOI: 10.1109/ASAP.2016.7760807.(CrossRef)(Google Scholar)
[34]  Diniz, P., and G. Govindu. (2006). “Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit”. International Conference on Field Programmable Logic and Applications, 28-30 August, 2006, 1-4. New York: IEEE. DOI: 10.1109/FPL.2006.311302.(CrossRef)(Google Scholar)
[35]  Hickman, Brian, Andrew Krioukov, and Michael Schulte. (2007). “A Parallel IEEE P754 Decimal Floating-Point Multiplier”. 25th International Conference on Computer Design, 7-10 October, 2007, 56-62. New York: IEEE. DOI: 10.1109/ICCD.2007.4601916.(CrossRef)(Google Scholar)
[36]  Vazquez, A., E. Antelo, and P. Montuschi. (2007). “A New Family of High–Performance Parallel Decimal Multipliers”. 18th IEEE Symposium on Computer Arithmetic (ARITH '07), 25-27 June, 2007, 195-204. New York: IEEE.
[37]  Cowlishaw, Mike. (2002). “Densely Packed Decimal Encoding”. IEE Proceedings – Computers and Digital Techniques 149 (3): 102-104.
[38]  Baesler, Malte, Sven-Ole Voigt, and Thomas Teufel. (2010). “An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier”. International Conference on Field Programmable Logic and Applications. 31 August-2 September, 2010, 489-495. New York: IEEE. DOI 10.1109/FPL.2010.98. (CrossRef)(Google Scholar)
[39]  Kuang, Shiann-Rong, Jiun-Ping Wang, and Hua-Yi Hong. (2010). “Variable-Latency Floating-Point Multipliers for Low-Power Applications”. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (10): 1493-1497. DOI: 10.1109/TVLSI.2009.2025167.(CrossRef)(Google Scholar)
[40]  Abraham, Sumod, Sukhmeet Kaur, and Shivani Singh. (2015). “Study of Various High Speed Multipliers”. International Conference on Computer Communication and Informatics (ICCCI), 8-10 January, 2015, 1-5. New York: IEEE. DOI: 10.1109/ICCCI.2015.7218139.(CrossRef)(Google Scholar)
[41]  Vyas, Keerti, Ginni Jain, Vijendra K. Maurya, and Anu Mehra. (2015). “Analysis of an Efficient Partial Product Reduction Technique”. International Conference on Green Computing and Internet of Things (ICGCIoT), 8-10 October, 2015, 1-6. New York: IEEE. DOI: 10.1109/ICGCIoT.2015.7380417. (CrossRef)(Google Scholar)
[42]  George, Marcus, and Geetam Singh Tomar. (2015). “Hardware Design Procedure: Principles and Practices”. 5th International Conference on Communication Systems and Network Technologies, 4-6 April, 2015, 834 - 838. New York: IEEE. DOI: 10.1109/CSNT.2015.198.(CrossRef)(Google Scholar)
[43]  GS Tomar, Marcus George, “Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization”, Springers Wireless Personal Communication, Vol.98, No.4, pp.3554-3561, (2018).

CITATION

COPYRIGHT

© 2019 George Marcus Lloyde et al. Published by Global Vision Press. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 International License (CCBY4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.