Proper

Abstract

The production of circuit designs operating at low voltage for low power consumption is increasing as the market demand for efficient portable electronic equipments is increasing. Reduction in supply voltage leads to sub-threshold leakage current which is one of the main reason for static power consumption. Leakage power consumption is a major contribution of total power dissipation in Deep Sub-Micron (DSM) technology for CMOS circuit design. Leakage Power is determined during the standby mode of operation. In this paper a review of various methods and techniques which are used for reducing the leakage power in VLSI circuits is shown. The various leakage reduction techniques included are: MTCMOS, VTCMOS,Stack Effect, Sleepy Stack, LECTOR Approach, GALEOR Approach.