Analysis of Oscillation Condition of CMOS Oscillation Network Using Tri-State Circuit
AUTHORS
Hyun-soo Kim,Dept. of Electronic Engineering, Hallym University, 1 Hallymdaehak-gil, Chuncheon, Gangwon-do, KOREA
Sung-Gu Kim,Research Institute of Informatic and Electronic Engineering, Hallym University 1, Hallymdaehak-gil, Chuncheon, Gangwon-do, KOREA
Gyu Moon,
ABSTRACT
We propose a GHz-band cellular oscillation / non-oscillation network circuit design with tri-state addition. An oscillator that can be used as a high-speed clock signal generator / distributor has a structure composed of a plurality of cells of a simple ring oscillator type. When tri-state is added, oscillation / non-oscillation can be controlled by enable signal, and power consumption is minimized through LPM mode and shutdown mode as well as synchronization problem due to delays between ultra-high speed semiconductor clock signals. In the CON structure, the number of tri-state requests is compared for three cases and the minimum required number is obtained. The simulation of the spectral characteristic curve of an oscillator with a 3.5V 0.46um CMOS N-well parameter parameter was verified and the maximum frequency was measured at 2.78GHz.
KEYWORDS
Ring oscillator, CMOS oscillator / distributor, Tri-State, low power
REFERENCES
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